Evaluation and Comparison of Offset Compensation Techniques for a Multi-Stage Comparator

This paper presents the analysis and modeling of a low-offset multi-stage comparator applied for a high-resolution successive-approximation-register (SAR) analog-to-digital converter (ADC). The comparator is based on three preamplifiers that scale down the voltage from 5 V to 1.5 V. Techniques for compensating the input-referred offset are analysed using pream-plifier macromodel and posterior electrical implementation. The circuit, designed in 130 nm BCD technology, achieves a 95 % offset voltage reduction using output offset storage compensation in the first two preamplifiers, when compared to the comparator implemented with no compensation scheme.