Analysis of Factor Impacts on On-resistance for Power MOSFET Layout Design with Fully Automatic Flow

Due to technical limitations and lack of specialized tools, the optimization of power MOSFET layout is done manually by designers, which is a time-consuming and error-prone process. This work achieves the automation of full flow for power MOSFET layout design by Python, which includes the process of layout generation, parasitic extraction, and post-layout simulation. Also, this paper explores the factors that impact on the on-resistance in the layout of power MOSFET, including design factors and related factors. Based on this new fully automatic flow developed, the experiments were conducted and on-resistance data were obtained in the post-layout simulation. The experimental results are confirmed with the physical principle, which shows how factors impact on the on-resistance. This analysis will serve as a reference for the layout design of power MOSFET in the future work.