Experimental analysis of mismatch in electro-thermal device parameter within parallel connected SiC MOSFETs: Considerations for multi-chip power module design

This paper aims to investigate the current imbalance within parallel connected common-source configuration of SiC Power MOSFET switches using double pulse transient operation. Mismatches in electro-thermal parameters e.g., threshold voltage ($V_{th)}$ and uneven unintentional PCB parasitic inductances can result in uneven current sharing during the transient operation. The tests presented here were carried out using $3^{\mathrm{r}\mathrm{d}}$ generation 650 V, 49 A-45 m$\Omega$ discrete SiC power MOSFET devices connected in parallel which is representative of a mutli-chip power module architecture. Moreover, theoretical analysis presented here also demonstrates how parasitic inductances in different locations within the commutation loop will have different effects on transient current sharing.