SerDes Integrated Into the SpaceWire Interface Helps in Achieving Higher Data Rates

The growth of transfer data between subsystems onboard a satellite is imminent, and the SpaceWire (SpW) communication standard fits in the high-speed full duplex serial communication protocols with data rates up to 400 Mbit/s. SpW Intellectual Property (IP) cores integrated into radiation hardened by design (RHBD) field programmable logic array (FPGA) devices struggle to reach data rates of up to 300 Mbit/s and, depending on the FPGA type. Two devices connected with the SpW link exchange 4-bit control and 10-bit data SpW symbols. Most designs have a 1-bit or 2-bit serialization/deserialization (SerDes), where digital structures do not need a lot of processing power for encoding/decoding SpW symbols. Furthermore, encoding/decoding SpW symbols to/from a SerDes with more than two bits requires extra digital processing power. This article proposes SpW4Brave Register Transfer Level (RTL) architecture with the multibit SerDes component and the required steps for encoding/decoding SpW symbols. The proposed register transfer level SpW4Brave architecture integrated in NG-MEDIUM and NG-LARGE BRAVE FPGA can reach data rates up to 400 Mbit/s with the help of the SpaceWire IP Bank. It utilizes a SerDes component (20-bit deserialization, a 10-bit serialization unit) and an encoding/decoding component for the strobe signal.