An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors

In the modern era, FPGA-based soft-core processors have gained much attention in space applications due to their flexibility and ease of integration. In such applications, radiation can produce a Single Event Upset (SEU) in CMOS devices that may lead to severe errors in microprocessors. The instruction decoder is one of the most critical components of a microprocessor. Any error in the instruction decoder due to SEU may destroy the flow of the program, and it may lead to complete system failure. Hence, a novel parity-based fault-tolerant instruction decoder architecture is proposed for dual-core processors implemented on FPGAs. In case of occurrence of SEU, the instruction decoders of two cores are swapped for fault-masking against single-bit error. Looking at the increased adaptability of RISC-V ISA, the proposed fault-tolerant instruction decoder is integrated with an in-house designed RV32IM processor using Verilog HDL. Further, the proposed fault-tolerant processor architecture is prototyped on commercially available NEXYS4 DDR FPGA board by employing the soft error mitigation (SEM) IP core of Xilinx Inc. to inject SEU in real time to study the fault tolerance capability. The proposed design is compared with the state-of-the-art SEU mitigation approaches. The main advantage of the proposed architecture is that the LUT (Look up table) overhead is 167.06% less, and power overhead is 46.87% less compared to the conventional triple modular redundancy (TMR) approach to mitigate SEU. The proposed design is able to provide 71.2% fault tolerance compared to the unprotected design.