A 276–312-GHz (×12) Frequency Multiplier Chain With Milliwatt Level Output Power in 65-nm CMOS Technology

This letter presents a
$\times 12$
frequency multiplier chain (FMC) for IEEE 802.15.3d applications. The FMC consists of a double-balance self-mixing (DBSM) tripler, two push–push doublers, and several buffers. The proposed DBSM tripler exhibits decent unwanted harmonics rejection performance and provides better third harmonic power. The following doublers and buffers are carefully optimized to achieve a considerable output power. Implemented in a 65-nm CMOS technology, the FMC occupies a chip area of
$1.05\times1.5$
mm2 including all pads and consumes a dc power consumption of 195 mW with a 1.2-V supply. The FMC achieves a 0.8-dBm peak output power at 288 GHz and covers a bandwidth from 276 to 312 GHz.