An advanced FPGA-based processor and controller for the Next-Generation Precipitation Radar

The Next-Generation Precipitation Radar (PR-2) prototyped by NASA/JPL will depend heavily on high-performance digital processing to collect meaningful rain echo data. Using field-programmable gate arrays (FPGAs), we have developed for the PR-2 a pulse-compression processor and adaptive timing controller that will enable full on-board processing capabilities in a 14 and 36 GHz spaceborne radar. This paper describes some of the new technologies for the on-board processor, including a 40/spl times/10/sup 9/ op/s bit-serial filter attaining -60 dB range sidelobe performance, and an adaptive scanning control and timing unit (CTU) which yields a 7-fold increase in the radar's dwell time over areas of precipitation.