RV32IMF Five-Stage Pipeline Implementation with Interrupt and Random Number Generation Units

In this paper, a five-stage pipeline implementation of the RV32IMF instruction set is presented for distributed event-driven random calculations. The system consists of a network interface and an interrupt controller to handle the data communication within the Network-on-Chip, which connects multiple core processing units. The Network on Chip (NoC) architecture enhances the scalability of the system in terms of core count, which is hard to achieve with a bus-based architecture. Further, interrupts offer the advantage of facilitating time-critical message passing among cores. The proposed architecture was implemented and tested with Altera DE2 and DE5 FPGA boards.