Inverter Current Limit Logic based on the IEEE 2800-2022 Unbalanced Fault Response Requirements

This paper presents a current limit logic based on the technical minimum fault ride-through response requirements specified in the IEEE Std 2800-2022 for inverter-based resources. The current limit logic acts on the current references of a current-controlled inverter that is controlled in two dq reference frames; one representing the positive sequence and one representing the negative sequence. If any of the phase currents will exceed their limit based on the current references, the current components (i.e., the active and reactive, positive and negative sequence) are prioritized as specified in IEEE 2800-2022. The current limit logic is implemented in an electromagnetic transients simulation tool generic three-phase inverter model that can inject negative sequence current in response to unbalanced faults. Simulations of unbalanced faults in PSCAD™ show the current limit logic proposed meets the prioritization requirements and maximizes the current injection based on the control objective.