Harmonic Phasor Estimation based on Substation Edge Device Philosophy

This article presents the implementation of a Harmonic Phasor Estimator (HPE) using the Substation Edge Device (SED) philosophy. The chosen HPE is based on the DFT with a preprocessing step using the modified Spline interpolator. With this scheme it is possible to obtain accurate results with low computational effort. The algorithm is then implemented in real time on an industrial computer, whose architecture is based on substation 4.0 concepts, in particular, SED. The results presented show the quality of the estimations as well as present a practical example of an HPE implemented as a software task following the concepts of open, interoperable and expandable architecture.