Self-Writing xnor Magnetic Random Access Memory for Binary Neural Network Acceleration

A XNOR circuit is proposed using a spin-transfer torque magnetic random access memory (STT-MRAM) array for weight-stationary binarized neural network (BNN) acceleration. The proposed circuit allows the memory array to perform XNOR operations using a self-writing technique in that the previous state of the bit-cell is used to modify the current bit-cell content. The proposed self-writing technique re-utilizes the standard memory infrastructure and requires only two additional CMOS switches per column. Also, the non-volatility of the STT-MRAM reduces the XNOR computation as well as energy on non-writing XNOR computation. A
$64\,\, {}\times {}16$
in-MRAM XNOR macro is designed and evaluated using a compact magnetic tunnel junction (MTJ) model, targeting an implementation in a 14 nm technology node. Analysis indicates that the proposed design succeeds in reducing the energy by 26.7% while maintaining the conventional bit-cell structure.