Improving the Verification Step of Wesolowski’s Verifiable Delay Function using efficient Double Modular Exponentiation

A group of modern cryptographic techniques known as Verifiable Delay Functions (VDFs) guarantees that a user has to spend a specific amount of time (evaluation step). Irrespective of the computation capacity of the system, the evaluation step will take a specified a mount of time when executed in a non-parallel environment. The verification step is independent of the evaluation step and must be performed in a small amount of time. Decentralized applications like blockchain and cloud computing welcome this feature of VDF. The VDF is used for verifying the executable programs and spam-prevention systems. In this work, we will optimize the verification phase of Wesolowski’s VDF. The provided double-modular exponentiation technique(SPDME) is efficient and uses algorithmic ways to avoid side-channel attacks. The proposed technique has been implemented in hardware.