Study of voltage margin of Gate oxide TDDB between AC and DC stress

In this work, TDDB characteristics in advanced nodes technology under AC stress and DC stress are investigated. The voltage margin between AC stress and DC stress is more than 100mV and 350mV under 1MHz AC stress and 100MHz, respectively. In addition to the studies of the effect of gate area and voltage on the voltage margin, the results indicate that the voltage margin can be extrapolated to a larger gate oxide area. However, the voltage margin is decreased with the V
stress
extrapolated from test voltage to operate voltage, which indicates that the voltage margin under operate voltage should be calculated based on the results of voltage margin under test voltage and fitting voltage coefficient.