A 960 MHz Area Efficient CMOS Power Amplifier with Integrated Active Load APD for RFID Application

In this work, we propose a CMOS power amplifier (PA) with an integrated active load based analog predistorter (APD). The technique employed improves the linearity of the PA by inducing an opposite responses between the APD and the main PA stages. The active load based APD also contributes to minimize the chip area consumed by the PA since it does not utilize a bulky passive inductor as the RF choke. The PA is intended for RFID operation at the frequency band of 960 MHz. In measurement, the input (S11) and output (S22) return losses achieved by the PA are -20.9 and -18.5 dB, respectively. The gain (S21) delivered is 17.8 dB. The peak OIP3 achieved is 29.5 dBm at 9 dBm output power. Despite the utilization of the active load for area reduction and active pre-distorter, the peak PAE achieved is 32%. The CMOS PA consumes DC power of 90 mW at maximum output power transmission of 14.5 dBm. The active load employed has contributed to the area minimization in which the total active area consumed by the fabricated PA is 0.6 mm × 1.5 mm.