Innovation Methodology for Foundry Array De-Scrambling Logical to Physical (L2P) Mapping

The "Address and Input/Output (IO) Array Scrambling" feature in the growing Foundry designed array has prominently restricted the accessibility to necessary failing memory logical information, causing failing memory cells are not being identifiable in the physical silicon. This reflected a significant gap in Failure Analysis (FA) root cause support level, which critically impacting high volume manufacturing yield enhancement and customer return FA support. This paper describes an effective method to overcome the limitation and restriction from Foundry Address and IO Array Scrambling by utilizing an array bitmap and presenting an automated solution to achieve Foundry array address de-scrambling and successfully performing Logical to Physical (L2P) on Foundry designed array to achieve yield improvement. Successful FA cases which benefited from this solution is presented. This Foundry Array De-scrambling L2P methodology can also be proliferated to future process nodes implementation as well.