No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits

Acquiring images of the layout of integrated circuits increases the demands on electron microscopy as the technology scaling continues. Each new chip generation makes producing stable and processable image quality more difficult. Currently, no automated, technology-agnostic solution supports the human operator in creating optimal layout images. Therefore, we propose an image quality assessment framework that determines the optimal microscope settings for each technology sample. We define the optimal settings as the minimum possible scan time, which still maintains the processability of the acquired images. The two implemented machine learning algorithms do not require a noise and distortion-free reference image. We compare both models on an updated version of the REFICS dataset and investigate their behavior for different noise types. Finally, we use our framework to fully recover the layout of a 28nm technology, reducing scan time by more than 95%.