Global Floorplanning via Semidefinite Programming

A major task in chip design involves identifying the location and shape of each major design block/module in the layout footprint. This is commonly known as floorplanning. The first step of this task is known as global floorplanning and involves identifying a location for each module that minimizes wire length and leaves sufficient area for each module. Existing global floorplanning methods either have a non-convex problem formulation, or have trivial global solutions with no guarantee on the quality of the result. Here, we model the global floorplanning as a Semi-Definite Programming (SDP) problem with a rank constraint. We replace the rank constraint with a direction matrix and convexify the problem, whose solution is shown to be a global optimum if an appropriate direction matrix is chosen. To calculate the direction matrix, a convex iteration algorithm is used where the problem is decomposed into two SDP sub-problems. Furthermore, we introduce a series of techniques that enhance the flexibility, accuracy, and efficiency of our algorithm. Design experiments demonstrate that our proposed method reduces the average wirelength up to 20% for different benchmarks and outline aspect ratios.