Unclamped Inductive Load Avalanche Capability of the BaSIC(DMM) Topology

The BaSIC(DMM) topology with SiC power MOSFETs has been demonstrated to enhance short-circuit withstand time with minimal impact on on-resistance and switching losses. SiC power MOSFETs must also survive avalanche breakdown under unclamped inductive load switching (UIS) conditions in applications. This paper provides the first analysis of the operation of the BaSIC(DMM) topology under UIS avalanche breakdown conditions. Two potential operating points for the Si DMM are identified with one providing good ruggedness while the other can lead to catastrophic failure of the SiC power MOSFET. The Si DMM operating point for the case of a practical implementation of the BaSIC(DMM) topology is experimentally demonstrated to result in the same rugged UIS avalanche breakdown performance observed for the internal SiC power MOSFET. The UIS avalanche ruggedness of the SiC power MOSFET is therefore not compromised by the BaSIC topology.