Comparative Analysis of Adiabatic Logic Circuits: Power Dissipation and Performance in FPGA and ASIC Implementations of ECRL and PFAL

This paper presents an investigation into the performance of adiabatic logic circuits, specifically PFAL and ECRL NAND and NOR gates, on FPGA and ASIC platforms. We evaluated power dissipation, area utilization, and reliability of analog, FPGA, and ASIC implementations. The power efficiency of PFAL circuits was significantly higher than that of ECRL circuits, particularly when MOSFET transistors were installed in NAND gates. The power dissipation of ECRL and PFAL circuits was significantly reduced for ASIC implementations compared to FPGA implementations. According to the results, adiabatic logic circuits such as ECRL and PFAL can be effectively incorporated into ASICs or optimized FPGA environments for energy-efficient computing. The development of alternative implementation techniques and circuit design refinements will be crucial to fully exploit the benefits of adiabatic logic across a variety of applications and technologies in the future. Our results show that our ASIC implementation of the adiabatic logic circuits outperforms traditional implementations in terms of the proposed design and achieves a performance of 0.16 ns with a
$0.8917\mu W$
on-chip power consumption at
$29.569\mu 2$
chip area.