Physical Design Implementation And Measurement Of Timing Metrics Of 32-Bit LEON SPARC Processor Used In Space Applications

There are numerous sequential processes involved in the design sequence of VLSI ICs or processors. It begins with the high-level synthesis, the functional design, and moves on to the manufacturing stage, the fabrication process. The method of converting a circuit's description into its physical layout is called physical design. The location of the cells and the associated pathways connecting them are described. Finding a layout with a smaller footprint and less overall wire length is a key challenge in VLSI physical design. The circuit's performance is directly impacted by the physical architecture. Performance, area, dependability, power and yield are the impacts that physical design is concerned with. To make physical design less complex, it is divided into smaller parts. In the beginning the circuit is divided into macro cells. In floor planning, the cells are assigned to specific location and are effectively positioned. After the placement process, global routing is carried out. It is possible to identify the errant paths that exist between each module, determine the precise path of the disconnected wires that run throughout the macro cell's channels. The layout compression comes last. In order to decrease the overall area, the design is compressed in this area along all dimensions. The physical design of a 32-bit LEON SPARC processor is created in the proposed effort to take up the least amount of space and operate as efficiently as possible that is employed in Defense and Space applications.