A Low Power and Reduced Delay SRAM Cell for Biomedical Applications

Reading operations are performed without the use of marginal printed circuit, the suggested circuit in this project is constructed using altered communication gate established SRAM cells for IOT uses. For biomedical systems to work in the sub threshold realm with flawless efficacy, numerous Kb of implanted memory is absolutely necessary. Given that they occupy 70% of the die, SRAMs dominate both overall silicon area and power consumption. This design offers increased data stability during read operations, lower area, decreased delay, and low power consumption. Using cadence virtuoso at 0.45 V, the SRAM cell is executed in 45nm and 90nm CMOS expertise.