FPGA Implementation of Image Super-Resolution Based on Bicubic Interpolation and CNN

In the field of GPU graphics processing, pixel performance is often the bottleneck of system performance. Reducing the load of the pixel engine is of great significance to improving the graphics performance of the chip. After rendering low-resolution images, the resolution is scaled to the desired size, which has become a widely used performance optimization method. Inspired by this approach, this paper proposes a method based on FPGA acceleration to scale 1K low-resolution (LR) images to 4K super-resolution (SR) images. The combination of bicubic interpolation and improved SRCNN is adopted to scale images. The algorithm structure is optimized through High-Level Synthesis (HLS), and the accelerated circuit is deployed on Field Programmable Gate Array (FPGA). Experimental result shows that FPGA achieves image super-resolution with lower latency than Intel Core i5- 8300H CPU and lower power consumption than NVIDIA GTX 2080Ti GPU.