A Novel Low Common-Mode Voltage DAC Switching Strategy for SAR ADCs

This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) with a conversion rate of 50 MS/s and proposes a low common-mode voltage fully differential switch switching scheme. The ADC employs a non-binary weighted non-split Sub-DAC capacitor structure and incorporates redundant bits to improve switch conversion speed and accuracy. During the switching process, only the reference voltage Vcm is utilized, with a variation range between 0 and Vcm. A comparison with traditional switching schemes demonstrates a 93% reduction in switch energy and an 83% decrease in area.In the SMIC 180nm CMOS process, utilizing an initial signal frequency of 24.26MHz, the ADC achieved a SNDR of 57.98dB and ENOB of 9.34 bits. Furthermore, the FOM for this ADC was measured to be 179.95 fJ/conversion-step.