Asynchronous Circular Buffers based on FIFO for Network on Chips

In multicore System-on-Chips (SoCs), Network on Chip (NoC) is utilized to facilitate on chip communication due to its benefits over bus-based topologies, specifically as chip sizes go smaller. Asynchronous, synchronous, or Globally Asynchronous and Locally Synchronous (GALS) NoC implementations are all possible. Although, efficiency of synchronous designs is confined by relies on slowest critical path and clock rates, it is essential to optimize every aspect of design. In this paper, an efficient asynchronous design is proposed for efficiently control FIFO buffers based on the time-consuming features of the system by preventing clock distribution issues and clock skew on chip. It also aids in improving efficiency of circular buffer by managing memory circularly and enables optimization solutions for infrequently utilized parts in system. Operation in terms of delays, offering effective performance as compared to low performance produced by synchronous counterpart, in addition to benefit of lower power consumption. In NoC routers, buffers are essential elements. In this paper, TSMC 180nm platform, Linear Technology Simulation program with integrated circuit emphasis (LT Spice) is employed to simulate a four-stage First in First out (FIFO) buffer depending on domino logic in asynchronous mode. The proposed asynchronous architecture maintains an operation in terms of throughput and latency while using 50% less power and minimal chip area than synchronous design, according to results.