A mmW Receiver Exploiting Complementary Current Reuse and Power Efficient Bias Point

This work explores the trade-offs of using transistor bias point scaling for power reduction in millimeter wave (mmW) circuits. Transistor bias point scaling through current reuse and moderate inversion biasing are common techniques at sub-6 GHz frequencies for power reduction. Very high transistor
$F_{\text {Max}}$
and symmetric n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS) devices in modern CMOS nodes enable the use of these techniques in the mmW regime. These techniques at mmW frequencies provide the same benefits found in lower frequency bands and also enable efficient and compact frequency doubler topologies. Using these techniques on a
$V$
-band receiver enables a low power consumption of 23 mW from a 1 V supply while operating at 67 GHz. This receiver performs excellently with an average noise figure of 4.4 dB with 15 GHz RF bandwidth (BW), 27 dB conversion gain, and −21.5 dB Input referred 1 dB compression point (P1dB). The receiver is implemented in a 45 nm RF CMOS process and consumes
$0.47 \text {mm}^{2}$
. The receiver’s low power consumption and excellent RF performance make it an ideal candidate for integration in large-scale analog or digital phased arrays.