Modulation of Ciss of a 4H-SiC Planar MOSFET With a Shorter Sidewall and a Thicker Gate

In this study, reducing the sidewall width of the 1200 V 4H-SiC planar power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) by 6.9% increases the input capacitance,
${C}_{\textit {iss}}$
, by approximately 6%, which is contributed by the increase of 13.5% in
$\text{Q}_{\text {GS}}$
directly. In order to increase the accuracy of calculation and dynamic characteristics, the equation of
${C}_{\textit {iss},\textit {sp}}$
might be counted in the sidewall capacitance,
${C}_{\textit {swal}{l}}$
, when the width is different from the interlayer dielectric thickness on the top of the gate. Then, the modified calculation result of 7% is almost consistent with the measured result of 6% and simulation result of 6.8% for
${C}_{\textit {iss},\textit {sp}}$
. In addition, the poly gate thickness between 400 nm and 800 nm can contribute extra change in
${C}_{\textit {iss},\textit {sp}}$
by 2-3% as well. Because of the reduction in the sidewall width, the die size is also reduced. The specific-on resistance is decreased by 17%, while exhibiting no significant change in reverse breakdown voltage.