110-GHz PLL Frequency Synthesizer With High-Efficiency Voltage-Controlled Oscillator

A high-efficiency frequency synthesizer operating at 110 GHz with an optimized voltage-controlled oscillator (VCO) is proposed in this article. The proposed synthesizer adopts a subsampling loop (SSL) to reduce the in-band phase noise under steady-state conditions. A new VCO design method is proposed to solve the low output efficiency problem in high-frequency oscillators. First, the maximum efficiency operation condition for a transistor in an oscillator is analyzed, and the method to construct the peripheral passive network with ideal devices is presented. Second, the requirement of the multiple power outputs for the VCO in a synthesizer and the loss of the passive devices are considered in the optimization process. Finally, quantitative analysis is performed with consideration of the real physical implementation and the parasitic influence of the VCO. Based on the above VCO design method, a 110-GHz frequency synthesizer with low phase noise and high efficiency is designed. The frequency synthesizer is implemented using 65-nm CMOS technology. It consumes only 14 mW of dc power to generate −6 dBm of output power. The experimental phase noise of the frequency synthesizer is t102.01 dBc/Hz at a 10-MHz offset.