CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

In this paper, a high-speed low-power CMOS synchronous up/down counter with a novel compact toggle flip-flop is proposed to achieve energy- and area-efficient speed enhancement. It adopts a high-speed local clock generation based on a single Manchester carry chain to improve counting speed. The counter embeds clock gating in the local clock generation to eliminate redundant power consumption. A compact toggle flip-flop is incorporated for device count and power reduction. Both the up- and down-counting capabilities are supported. A 16-bit proposed counter was fabricated in a 28-nm CMOS process. Performance evaluation results indicate that the proposed counters can provide up to 55% speed improvement as compared to conventional designs. It also indicates that up to 28% performance gain is obtained in terms of power-delay product compared to conventional clock-gated CMOS counters.