Experimental Method for Measuring the Jitter Sensitivity Function of SERDES IP Circuits

This work proposes an experimental method to measure the jitter sensitivity function (JSF) of SERDES IP circuits. The noise monitoring position of the test chip is designed to directly measure the on-chip power noise. By controlling the output amplitude of an external function generator through PDN impedance adjustment, a constant power noise can be applied to the circuit. Finally, the JSF can be evaluated by measuring the total jitter increase and on-chip power noise. The measurement results show that the HO value of the JSF measured from 10 MHz to 100 MHz is within the expected range considering the silicon’s corner conditions.