Insights Into the Grain Orientation Effect on Electromigration-Induced Failure in Solder Interconnects Through Phase Field Modeling

A notable development of electronic packaging technologies drives that the solder interconnects include a few numbers of grains, leading to the grain orientation dependence of interconnect performance and reliably. It was experimentally observed that the void formation followed by open failure of the solder interconnects under high electric current stressing are significantly affected by the grain orientation of the Sn-based solder, but the quantitative mechanics are yet to be further understood. In this work, a phase field model is proposed to investigate the void formation and electromigration-induced failure behavior at the interface of the solder interconnects, especially being capable of considering the grain orientation effect. We found that the formation, growth, and propagation velocities of voids at the interface are faster in the solder interconnects with the
${c}$
-axis of Sn perpendicular to the substrate. Moreover, it is demonstrated that more grains and a higher grain boundary diffusion coefficient promote void nucleation and growth, leading to an increase in electrical resistance and open failure. The diffusion flux analysis shows that the combined effect of surface, bulk, and grain boundary diffusions determines the magnitude of diffusion flux; thus, more diffusion channels or higher diffusion coefficients encourage void formation and propagation.