Case Study for Skewing MTNCL Circuits

The traditional approach to digital circuit design is synchronous, where one or more clock signals coordinate the operation of logic components globally. Although synchronous design is intuitive and often leads to high-performance circuits, it suffers from its own set of disadvantages including requiring substantial timing analysis for correct operation and generating significant electro-magnetic interference (EMI). Multi-Threshold NULL Convention Logic (MTNCL) is an ultra-low power quasidelay-insensitive (QDI) circuit design paradigm that utilizes local handshaking in lieu of a global clock to coordinate circuit operation. MTNCL circuits differ from synchronous circuits in several fundamental ways, one of which is that synchronous circuits are typically composed of unskewed gates with reasonably balanced rise and fall times, while MTNCL circuits could employ skewing in favor of the rise transition over the fall transition for more optimal implementation. Post-layout evaluation in TMSC 65nm technology demonstrates that constructing MTNCL circuits with skewed gates has the potential to enhance performance, reduce active energy consumption and static power consumption, and save area, all at the same time, regardless of whether the foremost goal is high performance or high energy efficiency. Further investigation only needs to evaluate the optimal degree of skewing employed.