X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture Model

To improve reconfigurable architectures' programmability, a CGRA named X4CP32 was proposed in early 2003. With two execution modes (programming execution mode and reconfigurable execution mode), X4CP32 offered an architectural model providing support to use the array through programming or configuration. In other words, a statical or dynamical procedure defines the processing elements' operations. This paper revisits this CGRA design using modern techniques and tools, notably the GEM5 simulator, the McPAT framework, and CACTI. Also, a hardware unit providing transparent and dynamic reconfiguration was incorporated. Furthermore, the design replaced an unknown and naive embedded microprocessor using RISC-V. Using a modern embedded processor, transparent and dynamic reconfiguration, and a thin array allows the design of a reconfigurable multicore able to execute up to 88% faster and with 55% less energy than a regular multicore. (Abstract)