Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis

Approximate circuits are emerging as an alternative to save area, delay, and power consumption in error-resilient applications such as machine learning, computer vision, and signal processing. This work presents an evaluation of a logic synthesis approach by exploring two- and multi-level topologies in approximating digital circuit design. In such a strategy, two-level (2L) approximated logic synthesis (ALS) unlocks robust function optimization, whereas multi-level (ML) ALS acts over the structure simplification. Experimental results of combined exploitation of 2L- and ML-ALS have shown improvement in the average area and delay optimization compared to the state-of-the-art ML-ALS for 5% of error rate, being a reduction of up to 37% in circuit area and up to 31% in delay for the same error constraint.