Synthesis of a Finite State Machine With Elementary Chains of States

Modified structure and method are proposed for synthesis of a combined finite state machine (CFSM) which forms the output functions of both types FSM – Mealy and Moore. Similar algorithms are used mainly for controlling the blocks of in-built systems in cases when the sensors that describe the system are not numerous, but it is necessary to perform certain sequences of microoperations. We consider a case when initial control algorithm is represented with a linear flowchart. Such flowcharts have a significant number of operator vertices, exceeding 75% of the total number of vertices. In the case of linear flowchart we propose to replace the register RG with a counter of states CT. It allows simplification of Boolean functions representing a combined FSM logic circuit. Also this allows to simplify the system of memory-excitation functions. The method uses existence of elementary linear chains of states in the initial flowchart. There is an example of synthesis and results of experimental study given in the article. The study of the proposed method based on the real control algorithm of the onboard computing device. Experiments and testing performed for various Intel (Altera) microchips. The studies carried out for different families of FPGAs, in different price ranges. A comparative analysis of time characteristics for the basic and proposed structures allows us to notice a tendency to some acceleration of the operation. In general, research results have shown that proposed structures of combined FSM can be useful for design of embedded systems.