An SRIO Bus-Based Implementation of a High-Speed Interface for Satellite 5G

The current low-orbiting satellite constellation is evolving towards a 5G communication system, and traditional satellite communication methods can hardly meet the needs of 5G applications. The implementation of 5G protocols requires the support of high speed and broad bandwidth data transmission. To solve the problems of low transmission rate, small bandwidth and poor reliability in large data volume transmission systems, a solution is proposed for the implementation of an SRIO bus-based onboard 5G protocol. The solution enables high-speed transfer of large amounts of data between the FPGA and the CPU. The design uses XILINX's SRIO IP core and the Rapid IO module embedded in the CPU to send, parse and receive the transmitted data. The design has been tested for accuracy and reliability with data transfer rates up to 3.5Gbps. It effectively solves the problem of high-speed and reliable transmission of large amounts of data between the FPGA and the CPU under the satellite 5G communication system. The solution has been successfully applied to the communication test project of the LEO constellation.