Hidden in Plain Sight: A Detailed Investigation of Selectively Increasing Local Density to Camouflage and Robustify Against Optical Probing Attacks

Modern chips have been demonstrated to be vulnerable to malicious Side-Channel Analysis (SCA) attacks that put Intellectual Property (IP) at risk. These SCA attacks and their countermeasures have been well-studied in literature. However, in recent years a non-invasive and laser-based SCA attack through the backside of chips, namely Optical Probing Attack (OPA), has emerged. OPA is effective in retrieving the chip's IP by reading out the transistors' terminal voltage. Some countermeasures to mitigate OPA have been proposed in the literature. However, these methods are too expensive to implement as they require a significant change in the fabrication process. These existing methods require a whole redesign of logic cells layout, characterization, synthesis, and place and route techniques which can be quite challenging. In this work, we investigate the effect of increasing the density around an important logic cell in the design, that needs to be secured against OPA. Our methodology requires only the standard cell library gates and can be easily integrated into the ASIC design flow. We found that increasing the local density of cells around an important logic cell can lead to a larger reflection. This can significantly help to camouflage the secure cell against OPA, as the reflection from the secure cell and the neighboring cells can be hard to differentiate. We show that this methodology can prove to be an effective countermeasure against OPA by performing detailed experiments of density versus reflection using nand and inverter cells. We exhaustively evaluated thousands of placement strategies with varying densities to show its efficacy against OPA.