Analysis of Non-Idealities in On-Chip Loopback Testing of Data Converters

The demanding linearity requirement of an on-chip ramp generator for ADC built-in self-test (BIST) has paved the way for alternative testing routes. Loopback testing has emerged as a substitute, in which another component, for example a DAC, in the same chip is used as the ramp stimulus, significantly reducing the cost incurred due to the need for an automatic test equipment (ATE). However, fault cancellations in loopback tests can lead to faulty units being undetected in production and thereby test escapes. This work analyzes non-idealities leading to test escapes in case of an ADC to DAC loop back test. Experiments have been performed on 2 types of DAC and one type of ADC using MAT LAB models. Results indicate that, with specific fault injections, out of a total of ten different DAC to ADC loop back configurations, six resulted in fault detection while four resulted in faults getting masked. A few test and design methods are also proposed to mitigate such fault masking.