Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation

Power, performance and area (PPA) are the three key differentiating factors in today's SoCs (System on-chips). To achieve best-in class PPA, complex processor cores using shared bus architecture typically use single physical memory across multiple logical memories to improve overall design efficiency. However, such an implementation imposes several limitations on enabling redundancy and repair support using on-chip memory test, redundancy analysis and repair implementation for the full range of memory space, resulting in a degraded repair coverage. This in turn could result in inferior yield and thereby increase cost margin for the product. In this paper, we propose a few novel strategies to seamlessly enable redundancy sharing across logical memories shared by a single physical memory to mitigate the limitation with conventional approaches. Additional schemes are proposed to resolve potential conflict conditions that could arise as a result of this redundancy sharing. Furthermore a comprehensive fault injection and repair verification methodology is shared to assess the efficacy of proposed methods. The experimental results by using the proposed solutions on two sample clusters on a large-scale design using shared bus architecture bridged a gap of 5-6% drop in repair coverage due to the shared physical memory implementation.