ASIC Implementation of Approximate Single Precision Floating Point Multiplier

In the age of Artificial intelligence, there is a need for a higher rate of data processing. Basic neural networks are composed of layers, each layer consists of neurons. Each neuron multiplies the inputs with its corresponding weights to get the output. The weight computation and output calculation require many floating-point multiplications. In image processing applications using neural networks, the exact value of output is not needed, a certain level of accuracy is accepted and will not hugely affect its functionality. Approximate designs will help in achieving functionality with approximation instead of exactness. Approximate multipliers introduce an error in the output making the circuit less complex and reducing the propagation delay. Adopting approximate floating-point multipliers can be beneficial as they need less space and power as compared to their exact counterparts. Exact arithmetic computation requires many gates consuming a large amount of power and calculation takes up much of the time. So, using approximate arithmetic computation can hugely affect the speed and power consumption of the system, and the overall complexity of the system is reduced. These approximate multipliers are used in such applications where the error can be tolerated to a certain level and does not affect the system’s overall functionality. In this paper exact single precision floating point multiplier and approximate single precision floating point multiplier using Vedic multiplier is proposed and implemented using Synopsys tool using 90nm technology.