SEGR Analysis of SJ_IGBT with High-k Gate Dielectrics for Radiation Environment

In this research, an examination of a single event gate rupture (SEGR) of an insulated gate bipolar transistor (IGBT), caused by a heavy ion striking the device at normal incidence on the middle of the gate was carried out. It has been witnessed that with use of combination of Sio
2
/Si
3
N
4
(10nm, 173nm) stacking as gate dielectrics, device shows better results towards the SEGR. The proposed gate engineering technique reduce the Si/Sio2 interface Electric field almost 50% as compared conventional device. Ion with different LET value has been investigated and it is found that device was susceptible up to LET = 98Mev.$\mathrm{cm}^{2}/\mathrm{mg}$ at $\mathrm{V}_{\mathrm{CE}}=100\mathrm{V}$. The above proposed technique helps to improve the device performance in the radiation rich environment.