Power gate resistance and its effect on loadline: Measurement and analysis on Intel® Core™ SoCs

Modern challenges of integrated power delivery is to provide ripple and noise free power with minimum I²R loss. With advancement in technology node, power gating is key feature of power management in low voltage environment. Gated side supply has higher loadline as compared to ungated side due to additional effective resistance of power gates. Power gate resistance becomes crucial in setting target voltage from voltage regulators for load IPs. In this paper, post silicon measurements are done on impedance profile of Intel® atom core on the gated and ungated side. Also, paper correlates the effective resistance of power gate obtained through simulated model and post silicon measurements. To round up the paper, power savings and loadline drop benefits obtained through post silicon measurements is shown and correlated it with simulation modelling.