Enhance Power and Temperature Control During Thermal Interference Events in Hybrid Core SoC Architecture

Modern-day microprocessors are designed with a lot of hybrid computing cores and Intellectual Property (IP) blocks (e.g., Memory controller, Cache-coherent Fabric/Ring, Image Processing Unit, Type-C Sub-system, System Agent (SA) domain, etc.) for the higher and improved performance needs of the end-user. Each of the IPs has multiple Digital Thermal Sensor Diodes (DTS) to check and report the temperature, which is used by system firmware to monitor and take suitable actions. The physical placement of these hybrid core IPs inside an SoC and their diodes are a few micrometers away from each other. There are cases wherein a particular IP in a module is under heavy load, resulting in higher temperatures. Due to the close physical proximity of the IPs, the power consumption on one IP causes cross-heating of the adjacent IPs which may result in the need to take action on the adjacent IPs to constrain the temperature of those adjacent IPs. Carefully designed experiments on Intel processors have shown a ∼30% temperature hike on adjacent cores that were not running any workload. The proposed solution described in this paper leverages knowledge of the relative priority of the IP blocks within a hybrid system by creating a newly proposed “IP cross heating” thermal threshold (Ti) for each IP block, where Ti is less than the maximum junction temperature (TjMax). As a preemptive action, before an IP reaches a temperature threshold associated with it, adjacent IPs that are a lower priority, are driven to lower power consumption in an attempt to prevent the higher priority IP from reaching a temperature where power reduction action is needed. This improves the performance of affected IPs with additional thermal headroom. To simplify the illustration, the example in this paper has been presented in terms of cores but the coverage of this paper does not limit to only cores, instead, the paper is covering all the IP blocks available within a microprocessor package.