Simplified Assembly of Through-Silicon-Via Integrated Ion Traps

The scalability of surface electrode ion traps has been progressively improved with the on-chip integration of conventional bulk components. Based on the development of through-silicon-via (TSV)-integrated ion trap, in this work, we further simplify the back-end assembly process by patterning a redistribution layer (RDL) onto a customized ceramic pin grid array (C-CPGA) package. This RDL has an internal connection with a CPGA pin on the back side, rerouting the electrical signal and facilitating the direct bonding of the TSV trap and CPGA. The patterned neighboring RDL has an averaged resistance of
$4.5\times 10^{12}\,\Omega $
, three orders of magnitude higher than that of the TSV trap itself. As compared to the previous assembly (glass interposer wire bonded to a conventional CPGA), a small parasitic capacitance increase of 0.1 pF of the C-CPGA is observed. Radio frequency (RF) electrical tests indicate that the trap on C-CPGA will not induce additional power loss. Meanwhile, due to the high thermal conductivity of ceramic materials, the heat dissipation capability of C-CPGA is boosted. The functionality of the TSV trap on C-CPGA is also demonstrated by trapping and laser cooling the 88Sr
$^{+}$
ions. The measured heating rate (21 quanta per millisecond for an axial frequency of 300 kHz) is comparable with the trap assembled in the previous approach. This indicates that the CPGA with built-in RDL is fully compatible with ion trapping applications, providing a new approach toward compact, flexible, and robust ion trap assembly.