3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET device is fully compatible with current Si technology platform using alternating anisotropic and isotropic dry etching process. The Ge NW pGAAFET presents an on-state current (ION) of
$166 ~\mu \text{A}/\mu \text{m}$
at
${\mathrm{ V}}_{\mathrm{ D}}\,\,=$
VG-VTH
$=\,\,-0.5$
V and shows minimum subthreshold swing (SSmin) of 79, 91 mV/dec, and ION/IOFF of
$3.03\times10\,\,^{\mathrm{ 5}}$
,
$3.4\times 10^{4}$
at
${\mathrm{ V}}_{\mathrm{ D}}\,\,=\,\,-0.05$
V and −0.5 V, respectively. The Si nFinFET presents an
${\mathrm{ I}}_{\mathrm{ ON}}$
of
$60.4 ~\mu \text{A}/\mu \text{m}$
at
${\mathrm{ V}}_{\mathrm{ D}}\,\,=$
VG-VTH = 0.5 V and shows
${\mathrm{ SS}}_{\min }$
of 91, 101 mV/dec, and ION/IOFF of
$9.01\times10\,\,^{\mathrm{ 4}}$
,
$5.62\times 10^{5}$
at
${\mathrm{ V}}_{\mathrm{ D}}\,\,=$
0.05 V and 0.5 V, respectively. The proposed CFET can simplify the process and shows promising potential for extending scaling beyond the technology node.