Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement

Realizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e., by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of standard single-phase converter modules. Further the low dc-link voltage level of typically
$400 \,{\rm {V}}$
(for a grid with
$230 \,{\rm {V}}_{\rm{rms}}$
line-to-neutral voltage) allows to employ high performance
$600 \,{\rm {V}}$
power semiconductors. The main drawback of this concept, however, is the fact that the time-varying single-phase input power only sums to a constant three-phase output power at the isolated dc output, such that large dc-link capacitor values are required in each module (in the range of several
$100 \,{\mu }{\rm{F}}$
for a
$6 \,{\rm{kW}}$
system), thereby limiting the achievable power density. It is known from literature that the dc-link energy buffering requirement
$ {\Delta} {E}_{\rm{dc}}$
can be reduced by means of a third-harmonic common-mode (CM) voltage injection modulation and this article identifies the optimal CM voltage waveform with respect to minimizing
$ {\Delta} {E}_{\rm{dc}}$
, i.e., reducing
$ {\Delta} {E}_{\rm{dc}}$
to the theoretical minimum by combining a brute-force evaluation of the time-domain CM voltage waveform with phase-symmetry considerations. Additionally, converter operation with minimum dc-link voltage and/or dc-link capacitor values is analyzed and a saturable grid current controller allowing operation of the PFC rectifier front-ends with the optimal CM voltage waveform is investigated. Experimental results with a
$6 \,{\rm{kW}}$
prototype system yield a reduction in
$ {\Delta} {E}_{\rm{dc}}$
by up to
$42{\%}$
(compared to conventional sinusoidal modulation), which closely matches the theoretical prediction. Also, PFC rectifier operation with a dc-link voltage level as low as
$285 \,{\rm {V}}$
(i.e., below the
$325 \,{\rm {V}}_\mathrm{pk}$
grid line-to-neutral voltage amplitude) and with ultra-low dc-link capacitor values is demonstrated.