Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures

The rise in quantum-computing systems, space electronics, and superconducting processors requires compatible cryogenic memories. The stringent operating conditions for these applications put additional constraints on the endurance and reliable operation of such memories. Ferroelectric-Field Effect Transistors (FeFETs) based on ferroelectric properties of the Hafnium Zirconium Oxide (HZO) can be an excellent choice for these systems. This requires a thorough characterization of FeFET at deep cryogenic temperatures. Also, the scalability of the FeFET to lower technology nodes implies a lower area and reduced leakage. In this work, we, therefore, fully characterize the 5 nm node Fe-FinFET from 10 K to 400 K. To this end, the underlying 5 nm node FinFET transistor is calibrated with experimental data from cryogenic temperatures to above-room temperatures. The material parameters of the Ferroelectric layer are also calibrated with reported measurement data. We propose that the reported endurance improvement of the HZO layer at cryogenic temperatures can improve the reliability of the Fe-FinFET. The observed wake-up and fatigue at higher temperatures are also nonexistent at cryogenic temperatures. Although the memory window is reduced at cryogenic temperature compared to room temperature, we can still hold multiple states. This is also verified through our simulations. Lastly, we demonstrate the variability in high and low threshold voltage (V
TH
) states due to extrinsic variation sources of the underlying transistor and ferroelectric material parameters. We observe a relatively lower variation at cryogenic temperature.