Arithmetic Logic Unit Circuit Designed for Near-Sensor Computing Architecture With Complementary Carbon Nanotube Field-Effect Transistor Technology

Novel circuits designed using carbon nanotube field-effect transistors (CNFETs) are gaining increasing attention because of advantages such as low-power operation, high operating speed, and support of advanced integration technology. In this work, we present a novel arithmetic logic unit (ALU) circuit that is designed entirely using complementary CNFETs. The ALU is intended to process a custom-made algorithm for a near-sensor computing architecture that requires low power and large bit width operation. We completed the ALU design using a large-scale complementary CNFET circuit (number of CNFETs in this circuit is 8160). The total power consumption of the ALU is 218.64 μW, which will satisfy the low-power requirements of the wireless sensor terminal. To verify the behavioral functionality of the circuit, we designed a lightweight binarized neural network and accomplished Modified National Institute of Standards and Technology (MNIST) standard handwritten digit recognition successfully through a register-transfer logic simulation using the proposed circuit and external logic. The accuracy of the algorithm can reach 90.20%. Our research demonstrates the feasibility of employing CNFET circuits in fields that involve the use of complex algorithms, e.g., image classification. The circuits based on the aligned-CNFET model is simulated and compared with MOSFET circuits based on a commercial silicon-based process design kit (PDK). Compared with MOSFET circuits, the aligned-CNFET circuits have an average increase in speed by more than 93% and an order-of-magnitude improvement in the power-delay product (PDP). The ALU and algorithm proposed here are suitable for near-sensor computing architectures for future smart sensors.