A sampling algorithm for digitally controlled boost PFC converters

Digital control of a boost power factor correction (PFC) converter requires sampling of the input current. As the input current contains a considerable amount of switching ripple and high frequency switching noise, the choice of the sampling instant is very important. To avoid aliasing without employing a (very) high sampling frequency, the sampling is synchronized with the pulse width modulation (PWM). Sampling algorithms employing this technique successfully reject the input current ripple but are not immune to the high frequency switching noise present on all sampled signals. Therefore, a new sampling algorithm, intended for center-based or symmetric PWM, is deduced with as most important features: switching noise immunity, straightforwardness, accurate measurement of the averaged input current and the need for only few processor cycles. The operating principle, design issues and a theoretical study of the input current error induced by the sampling algorithm due to sampling instant timing errors are derived. All theoretical results are validated experimentally by using a digitally controlled boost PFC converter switching at 50 kHz.