An All-Digital, 1.92–7.32 mV/LSB, 0.5–2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System

The on-chip droop in processor may cause a severe voltage reduction resulting in a need for high-speed and high-resolution on-chip voltage sensors. However, traditional voltage sensors hardly achieve high resolution at GHz-level sampling rate and require multiple cycles to obtain quantized results. Therefore, we propose an on-chip all-digital voltage sensor with dynamic PVT calibration for droop detection and a unified voltage monitor and scaling (UVMS) systems for efficiency improvement. We propose a balanced ring oscillator for high resolution and Nyquist counter-based encoder for GHz-level sampling. A light-weight dynamic PVT calibration using temperature sensor is proposed to resist the PVT variations and nonlinearity. Then, an adaptive prediction mechanism is proposed for 0-latency voltage detection. Fabricated in a 28nm CMOS technology, our voltage sensor achieves a high resolution of 7.32 mV/LSB at a 2 GS/s or 1.92 mV/LSB at a 0.5 GS/s sample rate with 0-latency and a calibration error of only 1 LSB. Implemented in a BNN accelerator, proposed UVMS compresses the margin and achieves a power gain of 37% - 57% at frequencies ranging from 31 MHz to 337 MHz.