FPGA Based Memory Security and Error Correction System for RISC-V Processor

With the rapid development of integrated circuits, the application of processor has become more and more widespread, and the information and data needs to be dealt with have become more complex, which brings great challenges to its security and dependability. As one of the most essential parts, memory affects the security and dependability of the processor. In terms of security, instruction set randomization is considered to be the effective means against code injection which is one of the common ways for hackers to attack memory. In terms of dependability, error correction codes are implemented to reduce soft errors like single-event upsets and multiple-bit upsets. These two methods are of great significance for improving the security and dependability of memory. With the rapid revolution of open-source hardware, RISCV instruction set architecture has been popular in academia and industry. However, the research on the security and dependability of processor based on RISC-V is still in its infancy. It is also hard for related studies to take into account little overhead in hardware resources, power consumption and performance while improving security or dependability. In this paper, we propose a FPGA based memory security and error correction systems for the RISC-V processor. The system integrates instruction set randomization and error correction codes to improve the security and dependability of processor while ensuring the performance of processor with less hardware overhead and power consumption.